Datasheet

PRINCIPLES OF OPERATION (1394b INTERFACE)
S5_LKON
LPS
PCLK
LREQ
D0–D7
CTL0–CTL1
Link-Layer
Controller
TSB41BA3D
LCLK_PMC
PINT
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
The TSB41BA3D is designed to operate with an LLC such as the Texas Instruments TSB82AA2 when the
BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the
respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This
interface is formally specified in the IEEE 1394b-2002 standard.
The interface to the LLC consists of the PCLK, LCLK_PMC, CTL0 – CTL1, D0 – D7, LREQ, PINT, LPS, and
S5_LKON terminals on the TSB41BA3D, as shown in Figure 22 .
Figure 22. PHY-LLC Interface
The LCLK_PMC terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal
and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC.
The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals
are synchronized to the rising edge of PCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB41BA3D and LLC.
The D0 – D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB41BA3D supports S400B, S200B, and S100B data transfers over the
D0 – D7 data bus. In S400B, S200B, and S100B operation, all Dn terminals are used.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request
access to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.
All data on LREQ is synchronous to LCLK_PMC.
The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and can be used to reset the PHY-LLC interface or to disable PCLK. The
S5_LKON terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either
LPS is inactive or the PHY register L bit is 0.
The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.
The TSB41BA3D normally controls the CTL0 – CTL1 and D0 – D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
Four operations can occur on the PHY-LLC interface: link service request, status transfer, data transmit, and
data receive. The LLC issues a service request to read or write a PHY register or to request the PHY to gain
control of the serial bus in order to transmit a packet.
The PHY can initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation whenever a packet is received from the serial bus.
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