Datasheet
PCLK
(a) (c)
(b)
CTL0, CTL1
D0–D7
LREQ
LPS
t
LPS_RESET
(d)
t
LPS_DISABLE
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ...............................................................................................................................................
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d. Interface restored. After the minimum t
RESTORE
time, the LLC can again assert LPS active. When LPS is
asserted, the interface is initialized as described in the following paragraph.
If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled. The PHY
disables the interface when it observes that LPS has been deasserted for t
LPS_DISABLE
. When the interface is
disabled, the PHY sets its CTL and D outputs as previously stated for interface reset, but also stops PCLK
activity. The interface is also placed into the disabled condition on a hardware reset of the PHY. Figure 20 shows
the timing for the interface disable.
When the interface is disabled, the PHY enters a low-power state if none of its ports are active.
Figure 20. Interface Disable
The sequence of events for disabling the PHY-LLC is as follows:
a. Normal operation. Interface is operating normally, with LPS active, PCLK active, status and packet data
reception and transmission via the CTL and D lines, and request activity via the LREQ line.
b. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µ s, terminates any request or interface bus
activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.
c. Interface reset. After t
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any interface bus
activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.
d. Interface disabled. If the LPS signal remains inactive for t
LPS_DISABLE
time, then the PHY terminates PCLK
activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state.
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