Datasheet

00
00 0000
(e)(d)(c)(b)(a)
01
00
000011
D0–D7
CTL0, CTL1
SYSCLK
00
Link Controls CTL and D
PHY High-Impedance CTL and D Outputs
Interface Reset and Disable
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
packet speed code is the same as the encoding for the received packet speed code (see Table 23 ). The link
cannot concatenate an S100 packet onto any higher-speed packet.
g. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status
transfer, receive operation, or transmit operation.
Figure 18. Cancelled/Null Packet Transmission
The sequence of events for a cancelled/null packet transmission is as follows:
a. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the
interface to the link.
b. Optional idle cycle. The link can assert at most one idle cycle preceding assertion of hold. This idle cycle is
optional; the link is not required to assert idle preceding hold.
c. Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of idle. These hold
cycle(s) are optional; the link is not required to assert hold preceding idle.
d. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle on
the CTL lines and then releasing the interface and returning control to the PHY. Note that the link can assert
idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert hold. It
is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold cycles are
asserted. This ensures that either the link or PHY controls the interface in all cycles.
e. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status
transfer, receive operation, or transmit operation.
The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface can be placed into a
reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface is
not operational (whether reset, disabled, or in the process of initialization), the PHY cancels any outstanding bus
request or register read request, and ignores any requests made via the LREQ line. Additionally, any status
information generated by the PHY is not queued and does not cause a status transfer on restoration of the
interface to normal operation.
The LPS signal can be either a level signal or a pulsed signal, depending on whether the PHY-LLC interface is a
direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY and
LLC, the LPS signal must be pulsed. In a direct connection, the LPS signal can be either a pulsed or a level
signal. Timing parameters for the LPS signal are given in Table 24 .
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