Datasheet
Receive
10
XX dnd0SPD
(a) (b)
FF (data-on)
D0–D7
CTL0, CTL1
SYSCLK
(c) (d)
TSB41BA3D
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............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009
a. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with
the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless
interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer
occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data is to
be sent in addition to any status information.
b. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.
The PHY can also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a
receive operation. The PHY asserts at least one idle cycle between consecutive status transfers.
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
receive on the CTL terminals and a logic 1 on each of the D bus terminals (data-on indication). The PHY
indicates the start of a packet by placing the speed code (encoded as shown in Table 23 ) on the D terminals,
followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet
has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All
received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not
included in the calculation of CRC or any other data protection mechanisms.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus
followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed
exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without
transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all
1s) on the D bus terminals, followed by Idle on the CTL terminals, without any speed code or data being
transferred. In all cases, in normal operation, the TSB41BA3D sends at least one data-on indication before
sending the speed code or terminating the receive operation.
The TSB41BA3D also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to
the LLC. This packet is transferred to the LLC just as any other received self-ID packet.
A. SPD = Speed code, see Table 23 . d0 – dn = Packet data
Figure 15. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:
a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status
transfer operation that is in progress so that the CTL lines can change from status to receive without an
intervening idle.
b. Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles
preceding the speed code.
c. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle
for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher that
which the link is capable of handling, then the link must ignore the subsequent data.
d. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on
the D lines with receive on the CTL lines for the remainder of the receive operation.
e. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
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