Datasheet

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Status Transfer

(a)

(b)

00 S[14:15]S[0:1]

D0, D1

CTL0, CTL1

SYSCLK

TSB41BA3D

SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ...............................................................................................................................................

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The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the

cycle start message under certain circumstances. The acceleration control request is therefore provided to allow

the LLC temporarily to enable or disable the arbitration acceleration enhancements of the TSB41BA3D during

the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over,

indicating that a cycle-start message is imminent, and then re-enables the enhancements when it receives a

cycle-start message. The acceleration control request can be made at any time and is immediately serviced by

the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-enabled, if the

EAA bit is set.

A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY

waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting

status(01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The

PHY maintains CTL = Status for the duration of the status transfer. The PHY might prematurely end a status

transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received before

the status transfer completes. The PHY continues to attempt to complete the transfer until all status information

has been successfully transmitted. At least one idle cycle occurs between consecutive status transfers.

The PHY normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by

the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request,

or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition

where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID

received packet. The status flags are considered to have been successfully transmitted to the LLC immediately

on being sent, even if a received packet subsequently interrupts the status transfer. Register contents are

considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status

transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not

yet completed.

Table 22 shows the definition of the bits in the status transfer, and Figure 14 shows the timing.

Table 22. Status Bits

BIT(s) NAME DESCRIPTION

0 Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as

defined in the IEEE 1394a-2000 standard). This bit is used by the LLC in the busy/retry state machine.

1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in

the IEEE 1394a-2000 standard). This bit is used by the LLC to detect the completion of an isochronous

cycle.

2 Bus reset Indicates that the PHY has entered the bus reset state

3 Interrupt Indicates that a PHY interrupt event has occurred. An interrupt event might be a configuration time-out,

a cable-power voltage falling too low, a state time-out, or a port status change.

4 – 7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC.

8 – 15 Data This field holds the register contents.

Figure 14. Status Transfer Timing

The sequence of events for a status transfer is as follows:

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