Datasheet
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ...............................................................................................................................................
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Table 16 shows the encoding for the request type.
Table 16. Request Type Encoding
LR1 – LR3 NAME DESCRIPTION
000 ImmReq Immediate bus request. On detection of idle, the PHY takes control of the bus immediately without arbitration.
Isochronous bus request. On detection of idle, the PHY arbitrates for the bus without waiting for a subaction
001 IsoReq
gap.
010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.
011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.
100 RdReg The PHY returns the specified register contents through a status transfer.
101 WrReg Write to the specified register
110 AccelCtl Enable or disable asynchronous arbitration acceleration
111 Reserved Reserved
For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in Table 17 .
Table 17. Bus Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1 – 3 Request type Indicates the type of bus request. See Table 16 .
Indicates the speed at which the PHY sends the data for this request. See Table 18 for the encoding of this
4 – 6 Request speed
field.
7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted.
Table 18 shows the 3-bit request speed field used in bus requests.
Table 18. Bus Request Speed Encoding
LR4 – LR6 DATA RATE
000 S100
010 S200
100 S400
All Others Invalid
NOTE:
The TSB41BA3D accepts a bus request with an invalid speed code and processes
the bus request normally. However, during packet transmission for such a request, the
TSB41BA3D ignores any data presented by the LLC and transmits a null packet.
For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 19 .
Table 19. Read Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1 – 3 Request type A 100 indicates this is a read register request.
4 – 7 Address Identifies the address of the PHY register to be read
8 Stop bit Indicates the end of the transfer (always 0)
For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 20 .
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