Datasheet

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)
S5_LKON
LPS
PCLK (SYSCLK)
LREQ
D0–D7
CTL0–CTL1
Link-Layer
Controller
TSB41BA3D
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
The TSB41BA3D is designed to operate with an LLC such as the Texas Instruments TSB12LV21B, TSB12LV26,
TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of operation for the
Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe
the operation of the PHY-LLC interface. This interface is formally defined in IEEE 1394a-2000, Section 5A.
The interface to the LLC consists of the PCLK, CTL0 – CTL1, D0 – D7, LREQ, LPS, and S5_LKON terminals on
the TSB41BA3D, as shown in Figure 12 .
Figure 12. PHY-LLC Interface
The PCLK terminal provides a 49.152-MHz interface system clock. All control and data signals are synchronized
to and sampled on the rising edge of PCLK. This terminal serves the same function as the SYSCLK terminal of
1394a-2000-compliant PHY devices.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB41BA3D and LLC.
The D0 – D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB41BA3D supports S100, S200, and S400 data transfers over the
D0 – D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only the D0 – D3
terminals are used; and in S400 operation, all D0 – D7 terminals are used for data transfer. When the
TSB41BA3D is in control of the D0 – D7 bus, unused Dn terminals are driven low during S100 and S200
operations. When the LLC is in control of the D0 – D7 bus, unused Dn terminals are ignored by the TSB41BA3D.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request
access to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.
The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC and can be used to reset the PHY-LLC interface or to disable PCLK. The
S5_LKON terminal sends a wake-up notification to the LLC or external circuitry and indicates an interrupt to the
LLC when either LPS is inactive or the PHY register L bit is 0.
The TSB41BA3D normally controls the CTL0 – CTL1 and D0 – D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
Four operations can occur on the PHY-LLC interface: link service request, status transfer, data transmit, and
data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain
control of the serial bus in order to transmit a packet, or to control arbitration acceleration.
The PHY can initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation whenever a packet is received from the serial bus.
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