Datasheet

Power-Class Programming
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
Table 8. Page 1 (Vendor ID) Register Configuration
BIT POSITION
Address
0 1 2 3 4 5 6 7
1000 Compliance
1001 Reserved
1010 Vendor_ID0
1011 Vendor_ID1
1100 Vendor_ID2
1101 Product_ID0
1110 Product_ID1
1111 Product_ID2
Table 9. Page 1 (Vendor ID) Register Field Descriptions
FIELD SIZE TYPE DESCRIPTION
Compliance 8 Rd Compliance level. For the TSB41BA3D, this field is 02h, indicating compliance with the 1394b-2002
specification.
Vendor_ID 24 Rd Manufacturer's organizationally unique identifier (OUI). For the TSB41BA3D, this field is 08_00_28h (Texas
Instruments) (the MSB is at register address 1010b).
Product_ID 24 Rd Product identifier. For the TSB41BA3D, this field is 83_30_03h (the MSB is at register address 1101b).
The vendor-dependent page provides access to the special control features of the TSB41BA3D, as well as
configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to
the Page_Select fieldin base register 7. Table 10 shows the configuration of the vendor-dependent page and
Table 11 shows the corresponding field descriptions.
Table 10. Page 7 (Vendor-Dependent) Register Configuration
BIT POSITION
Address
0 1 2 3 4 5 6 7
1000 Reserved Reserved
1001 Reserved for test
1010 Reserved for test
1011 Reserved for test
1100 Reserved for test
1101 Reserved for test
1110 SWR Reserved for test
1111 Reserved for test
Table 11. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD SIZE TYPE DESCRIPTION
SWR 1 Rd/Wr Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (same effect as momentarily
asserting the RESET terminal low). This bit is always read as a 0.
The S2_PC0, S1_PC1, and S0_PC2 terminals can be used in some port speed/mode selections to set the
default value of the power-class indicated in the pwr field (bits 21 – 23) of the transmitted self-ID packet.
Descriptions of the various power-classes are given in Table 12 . The default power-class value is loaded
following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in
register 4.
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