Datasheet
TSB41BA3D
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............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009
Table 5. Base Register Field Descriptions (continued)
FIELD SIZE TYPE DESCRIPTION
STOI 1 Rd/Wr
State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus
reset to occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit.
If the STOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the
S5_LKON output to notify the LLC to service the interrupt.
PEI 1 Rd/Wr Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for
any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt
enable (WDIE) bit is set, then the PEI bit is set to 1 at the start of resume operations on any port. This bit
is reset to 0 by hardware reset, or by writing a 1 to this register bit.
EAA 1 Rd/Wr
Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation,
and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus
reset. This bit has no effect when the device is operating in 1394b mode.
NOTE: The use of accelerated arbitration is completely compatible with networks containing legacy IEEE
Std 1394-1995 PHYs. The EAA bit is set only if the attached LLC is 1394a-2000-compliant. If the LLC is
not 1394a-2000 or 1394b-2002-compliant, then the use of the arbitration acceleration enhancements can
interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets.
EMC 1 Rd/Wr
Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by
hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in
1394b mode.
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy
IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be
1394a-2000 or 1394b-2002-compliant.
Max Legacy 3 Rd Maximum legacy-path speed. This field holds the maximum speed capability of any legacy node
SPD (1394a-2000 or 1394-1995-compliant) as indicated in the self-ID packets received during bus initialization.
Encoding is the same as for the PHY_SPEED field (but limited to S400 maximum).
BLINK 1 Rd Beta-mode link. This bit indicates that a Beta-mode-capable link is attached to the PHY. This bit is set by
the BMODE input terminal on the TSB41BA3D.
Bridge 2 Rd/Wr This field controls the value of the bridge (brdg) field in self-ID packet. The power reset value is 0. Details
for when to set these bits are specified in the IEEE 1394.1 bridging specification.
Page_Select 3 Rd/Wr Page_Select. This field selects the register page to use when accessing register addresses 8 through 15.
This field is reset to 0 by a hardware reset and is unaffected by bus reset.
Port_Select 4 Rd/Wr Port_Select. This field selects the port when accessing per-port status or control (for example, when one
of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is
reset to 0 by hardware reset and is unaffected by bus reset.
The port status page provides access to configuration and status information for each of the ports. The port is
selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base
register 7. Table 6 shows the configuration of the port status page registers, and Table 7 gives the corresponding
field descriptions. If the selected port is unimplemented, then all registers in the port status page are read as 0.
Table 6. Page 0 (Port Status) Register Configuration
BIT POSITION
Address
0 1 2 3 4 5 6 7
1000 Astat Bstat Ch Con RxOK Dis
1001 Negotiated_speed PIE Fault Standby_fault Disscrm B_Only
1010 DC_connected Max_port_speed LPP Cable_speed
1011 Connection_unreliable Reserved Beta_mode Reserved
1100 Port_error
1101 Reserved Sleep_Flag Sleep_enable Loop_disable In_standby Hard_disable
1110 Reserved
1111 Reserved
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