Datasheet
SLLS418I − JUNE 2000 − REVISED DECEMBER 2004
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
interface reset and disable (continued)
Table 21. LPS Timing Parameters
PARAMETER DESCRIPTION MIN MAX UNIT
T
LPSL
LPS low time (when pulsed) (see Note 5) 0.09 2.6 µs
T
LPSH
LPS high time (when pulsed) (see Note 5) 0.021 2.6 µs
LPS duty cycle (when pulsed) (see Note 6) 20% 55%
T
LPS_RESET
Time for PHY to recognize LPS deasserted and reset the interface 2.6 2.68 µs
T
LPS_DISABLE
Time for PHY to recognize LPS deasserted and disable the interface 26.03 26.11 µs
T
RESTORE
Time to permit optional isolation circuits to restore during an interface reset 15 23
†
µs
T
CLK_ACTIVATE
Time for SYSCLK to be activated from reassertion of LPS
PHY not in low-power state 60 ns
T
CLK_ACTIVATE
Time for SYSCLK to be activated from reassertion of LPS
PHY in low-power state 5.3 7.3 ms
†
The maximum value for T
RESTORE
does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before
LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less
than T
LPS_DISABLE
.
NOTES: 5. The specified T
LPSL
and T
LPSH
times are worst-case values appropriate for operation with the TSB41AB3. These values are broader
than those specified for the same parameters in the 1394a-2000 Supplement (i.e., an implementation of LPS that meets the
requirements of 1394a-2000 operates correctly with the TSB41AB3).
6. A pulsed LPS signal must have a duty cycle (ratio of T
LPSH
to cycle period) in the specified range to ensure proper operation when
using an isolation barrier on the LPS signal (e.g., as shown in Figure 8)
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request
activity. When the PHY observes that LPS has been deasserted for T
LPS_RESET
, it resets the interface. When
the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity
on the LREQ signal. The timing for interface reset is shown in Figure 22 and Figure 23.
SYSCLK
ISO
(Low)
(a) (c)
(b)
CTL0, CTL1
D0−D7
LREQ
LPS
(d)
T
LPS_RESET
T
RESTORE
T
LPSL
T
LPSH
Figure 22. Interface Reset, ISO Low