Datasheet


    
SLLS418I − JUNE 2000 − REVISED DECEMBER 2004
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
output differentiation (continued)
011000 010
LHZ0ZZ LHZ
Logic State
Signal Level
Figure 14. Signal Transformation for Digital Differentiation
The TSB41AB3 implements differentiation circuitry functionally equivalent to that shown in Figure 15 on the
bidirectional CTL0–CTL1and D0–D7 terminals. The TSB41AB3 also implements an input hysteresis buffer on
the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also implement
similar output differentiation and input hysteresis circuitry on its CTL and D terminals, and output differentiation
circuitry on its LREQ terminal.
DIn
To/From Internal
Device Logic
DOut
ISO
OutEn
Init
SysClk
DQ
D
QD
QD
3-State Output
Driver
Input Buffer With
Hysteresis
Figure 15. Input/Output Differentiation Logic