Datasheet


    
SGLS122C − JULY 2002 − REVISED JUNE 2008
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
TPA2+
TPA2−
TPB2+
TPB2−
TPA1+
TPA1−
TPB1+
TPB1−
TPA0+
TPA0−
TPB0+
TPB0−
Cable Port 0
Cable Port 1
Cable Port 2
CPS
LPS
ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D5
D1
D2
D3
D4
D6
D7
PC0
PC1
C/LK0N
PC2
RESET
PD
Bias Voltage
and
Current Generator
R0
R1
TPBIAS0
TPBIAS1
TPBIAS2
Link
Interface
I/O
XI
XO
FILTER0
FILTER1
Received Data
Decoder/Retimer
Arbitration
and Control
State Machine
Logic
Transmit
Data
Encoder
Crystal Oscillator,
PLL System,
and
Clock Generator