Datasheet
SGLS122C − JULY 2002 − REVISED JUNE 2008
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for resetting the PHY-LLC interface when it is in the differentiated mode of operation
(ISO
terminal is low) is as follows:1
a. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet
data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
b. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface
bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should
terminate any output signal activity such that signals end in a logic 0 state).
c. Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY
terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface
is now in the reset state.
d. Interface restored. After the minimum T
RESTORE
time, the LLC may again assert LPS active. (The
minimum T
RESTORE
interval provides sufficient time for the biasing networks used in Annex J type
isolation barrier circuits to stabilize and reach a quiescent state if the isolation barrier has somehow
become unbalanced.) When LPS is asserted, the interface initializes as described below.
SYSCLK
ISO
(high)
(a) (c)
(b)
CTL0, CTL1
D0 − D7
LREQ
LPS
(d)
T
LPS_RESET
T
RESTORE
Figure 24. Interface Reset, ISO High