Datasheet

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    
SGLS122C − JULY 2002 − REVISED JUNE 2008
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
LLC service request (continued)
The 3-bit request speed field used in bus requests is shown in Table 15.
Table 15. Bus Request Speed Encoding
LR4-LR5 DATA RATE
000 S100
010 S200
100 S400
All Others Invalid
NOTE:
The TSB41AB3 accepts a bus request with an invalid speed code and process the bus request
normally. However, during packet transmission for such a request, the TSB41AB3 ignores any data
presented by the LLC and transmits a null packet.
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16.
Table 16. Read Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1-3 Request type A 100 indicates this is a read register request
4-7 Address Identifies the address of the PHY register to be read
8 Stop bit Indicates the end of the transfer (always 0)
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17.
Table 17. Write Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1-3 Request type A 101 indicates this is a write register request
4-7 Address Identifies the address of the PHY register to be written to
8-15 Data Gives the data that is to be written to the specified register address
16 Stop bit Indicates the end of the transfer (always 0)
For an acceleration control request the Length of the LREQ data stream is 6 bits as shown in Table 18.
Table 18. Acceleration Control Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1-3 Request type A 110 indicates this is an acceleration control request
4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0
5 Stop bIt Indicates the end of the transfer (always 0)