Datasheet


    
SGLS122C − JULY 2002 − REVISED JUNE 2008
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
(continued)
thermal characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
θJA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivity T
I
recommended test board, chip soldered or greased to
19.04 °C/W
R
θJC
Junction-to-case thermal resistance
recommended test board, chip soldered or greased to
thermal land with 2 oz. copper
0.17 °C/W
R
θJA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivity T
I
recommended test board with thermal land but no solder
31.52 °C/W
R
θJC
Junction-to-case thermal resistance
recommended test board with thermal land but no solder
or grease thermal connection to thermal land with 2 oz
.
copper
0.17 °C/W
R
θJA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivity JEDEC test
49.17 °C/W
R
θJC
Junction-to-case thermal resistance
Board mounted, no air flow, high conductivity JEDEC test
board with 1 oz. copper
3.11 °C/W
switching characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Jitter, transmit Between TPA and TPB ±0.15 ns
Skew, transmit Between TPA and TPB ±0.1 ns
t
r
TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns
t
f
TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns
t
su
Setup time, CTL0, CTL1, D1−D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns
t
h
Hold time, CTL0, CTL1, D1−D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns
t
d
Delay time, SYSCLK to CTL0, CTL1, D1−D7 50% to 50%, See Figure 3 2
†
ns
†
Test conditions: V
CC
= 3.3 V, T
A
= 25°C
0.10
1.00
10.00
100.00
1000.00
100.0 110.0 120.0 130.0 140.0 150.0 160.0
Estimated Life (Years)
Continuous T
J
(5C)
Wirebond Voiding Fail Mode
Electromigration Fail Mode
NOTES: A. See previous pages for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
C. Enhanced product disclaimer applies.
Figure 1. Operating Life Derating Chart