Datasheet
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
TYPE
I/O
DESCRIPTION
NAME NO.
TYPE
I/O
DESCRIPTION
DV
DD
25, 26, 61,
62
Supply − Digital circuit power terminals. A combination of high frequency decoupling capacitors near each
terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are separated from PLLV
DD
and AV
DD
inside the device to provide noise isolation. They should be tied at a low-impedance point on the
circuit board.
FILTER0
FILTER1
54
55
CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter
required for stable operation of the internal frequency multiplier PLL running from the crystal
oscillator. A 0.1-µF ±10% capacitor is the only external component required to complete this filter.
ISO 23 CMOS I Link interface isolation control input. This terminal controls the operation of output differentiation
logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented
between the TSB41AB2 and LLC, the ISO terminal should be tied low to enable the differentiation
logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is
implemented, the ISO
terminal should be tied high through a pullup to disable the differentiation
logic. For additional information refer to TI application note Galvanic Isolation of the IEEE
1394−1995 Serial Bus, literature number SLLA011.
LPS 15 CMOS I Link power status input. This terminal is used to monitor the active/power status of the link layer
controller and to control the state of the PHY−LLC interface. This terminal should be connected
through a 10-kΩ resistor either to the V
DD
supplying the LLC, or to a pulsed output which is active
when the LLC is powered (see Figure 8). A pulsed signal should be used when an isolation barrier
exists between the LLC and PHY (see Figure 9).
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128
SYSCLK cycles), and is considered active otherwise (that is, asserted steady high or an
oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns
to assure that a high is observed by the PHY.
When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a
low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state
and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a
low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC
interface is placed into the disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set
to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared
to 0.
LREQ 1 CMOS I LLC request input. The LLC uses this input to initiate a service request to the TSB41AB2. Bus
holder is built into this terminal.
PC0
PC1
PC2
20
21
22
CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the
power class indicated during self-ID. Programming is done by tying these terminals high or low.
See Table 9 for encoding.
PD 14 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active
monitor circuits, which control the CNA output. Asserting the PD input high also activates an
internal pulldown on the RESET terminal so as to force a reset of the internal control logic. (PD
is provided for legacy compatibility and is not recommended power management in place of IEEE
1394a-2000 suspend/resume LPS and C/LKON features.)
PLLGND 57, 58 Supply − PLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit
board ground plane.
PLLV
DD
56 Supply − PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each
terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. This supply terminal is separated from DV
DD
and AV
DD
inside
the device to provide noise isolation. It should be tied at a low-impedance point on the circuit
board.