Datasheet

 
   

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Received Data
Decoder/Retimer
Link
Interface
I/O
Arbitration
and Control
State Machine
Logic
Bias Voltage
and
Current
Generator
Transmit Data
Encoder
Cable Port 0
Crystal
Oscillator,
PLL System,
and Clock
Generator
TPA0+
CPS
TPA0−
TPB0+
TPB0−
XI
XO
FILTER0
FILTER1
LPS
ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
C/LKON
R0
R1
TPBIAS0
PD
RESET
TPBIAS1
Cable Port 1
TPA1+
TPA1−
TPB1+
TPB1−