Datasheet
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
crystal selection (continued)
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing
noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and
two load capacitors should be considered as a unit during layout. The crystal and load capacitors should be
placed as close as possible to one another while minimizing the loop area created by the combination of the
three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the
effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors)
should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Figure 11
depicts a layout that meets these guidelines.
C9 C10
X1
Figure 11. Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for the design be to measure the frequency of
the SYSCLK output of the PHY. This should be done with a frequency counter with an accuracy of six digits or
better. If the SYSCLK frequency is more than the crystal tolerance from 49.152 MHz, the load capacitance of
the crystal may be varied to improve frequency accuracy. If the frequency is too high, add more load
capacitance; if the frequency is too low, decrease load capacitance. Typically, changes should be done to both
load capacitors (C9 and C10 above) at the same time, and both should be of the same value. Additional design
details and requirements may be provided by the crystal vendor. For more information, see Selection and
Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers, TI literature number SLLA051.
EMI guidelines
For electromagnetic interference (EMI) guidelines and recommendations, send a request via email to:
1394-EMI@list.ti.com
designing with the PowerPAD package
The TSB41AB2 is housed in a high performance, thermally enhanced, 64-terminal PAP PowerPAD package.
Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD,
which is an exposed metallic pad on the bottom of the device, is a thermal and electrical conductor. This exposed
pad is connected inside the package to the substrate of the silicon die, it is not connected to any terminal of the
package. Therefore, if not implementing PowerPAD
PCB features, the use of solder masks (or other assembly
techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection
etches or vias under the package. The recommended option, however, is to not run any etches or signal vias
under the device, but to have only a grounded thermal land as explained below. Although the actual size of the
exposed die pad may vary, the minimum size required for the keep-out area of the 64-terminal PAP PowerPAD
package is 8 mm × 8 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper (see Figure 12),
underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package
being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal
land may or may not contain numerous thermal vias depending on PCB construction.