Datasheet

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   

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
crystal selection (continued)
The following are some typical specifications for crystals used with the physical layers from TI in order to achieve
the required frequency accuracy and stability:
D Crystal mode of operation: Fundamental
D Frequency tolerance at 25°C: Total frequency variation for the complete circuit is 100 ppm. A crystal with
±30-ppm frequency tolerance is recommended for adequate margin.
D Frequency stability (over temperature and age): A crystal with ±30-ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for
error introduced by board and device variations. Trade-offs between frequency tolerance and stability may
be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency
tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30
ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the
frequency variation.
D Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (C
L
) is a function of not only the
discrete load capacitors, but also board layout and circuit. It may be necessary to intermittently select
discrete load capacitors until the SYSCLK output is within specification. It is recommended that load
capacitors with a maximum of ±5% tolerance be used.
As an example, for the OHCI + 41LV02 + evaluation module (EVM), which uses a crystal specified for 12-pF
loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular
board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals
[C
(PHY)
] and the loading of the board itself [C
(BD)
]. The value of C
(PHY)
is typically about 1 pF, and C
(BD)
is
typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors
C9 and C10 combine as capacitors in series so that the total load capacitance is:
C
L
+
ƪ
(
C9 C10
)
(C9 ) C10)
ƫ
) C
(PHY)
) C
(BD)
24.576 MHz
X1 C
(PHY)
+ C
(BD)
XI
XO
C9
C10
Figure 10. Load Capacitance for the TSB41AB2 PHY
(1)