Datasheet

 
   

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TPA+
TPB+
TPA−
TPB−
56 Ω
Figure 1. Test Load Diagram
t
su
t
h
SYSCLK
Dx, CTLx,
LREQ
Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms
t
d
SYSCLK
Dx, CTLx
Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms