Datasheet

 
   

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
thermal characteristics
PARAMETER TEST CONDITIONS
†
MIN TYP MAX UNIT
R
θJA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivit
y
TI-recommended test board, chip soldered or
26
°C/W
R
θJC
Junction-to-case-thermal resistance
TI-recommended test board, chip soldered or
greased to thermal land with 1 oz. copper
5.9
°C/W
R
θJA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivit
y
TI-recommended test board with thermal land, but no
58.57
°C/W
R
θJC
Junction-to-case thermal resistance
TI-recommended test board with thermal land, but no
solder or grease thermal connection to thermal land
with 1 oz. copper
5.9
°C/W
R
θJA
Junction-to-ambient thermal resistance
Board mounted, no air flow, low conductivity JEDEC
60.08
°C/W
R
θJC
Junction-to-case thermal resistance
Board mounted, no air flow, low conductivity JEDEC
test board with 1 oz. copper
5.9
°
C/W
†
Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions.
switching characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Jitter, transmit Between TPA and TPB ± 0.15 ns
Skew, transmit Between TPA and TPB ± 0.1 ns
t
h
Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns
t
su
Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns
t
d
Delay time, SYSCLK to CTL0, CTL1, D0–D7 50% to 50%, See Figure 3 2
‡
ns
t
r
TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns
t
f
TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns
‡
Test Conditions: 3.3 V
CC
, T
A
= 25°C