Datasheet

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SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted) (continued)
device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
See Note 2 71
I
DD
Supply current
See Note 3 69
mA
I
DD
Supply current
See Note 4 59
I
DD(ULP)
Supply current, ultralow-power mode
V
DD
= 3.3 V, T
A
= 25°C,
Port disabled, PD = 0 V,
LPS = 0 V
150 µA
I
DD(PD)
Supply current, power-down mode
PD = V
DD
,V
DD
= 3.3 V,
T
A
= 25°C
150 µA
V
(TH)
Power status threshold, CPS input
400-k resistor
4.7 7.5 V
High-level output voltage, CTL0, CTL1,
V
DD
= 2.7 V, I
OH
= −4 mA 2.2
V
OH
High-level output voltage, CTL0, CTL1,
D0D7, CNA, C/LKON, SYSCLK outputs
V
DD
= 3 V to 3.6 V,
I
OH
= −4 mA
2.8
V
V
OL
Low-level output voltage, CTL0, CTL1,
D0D7, CNA, C/LKON, SYSCLK outputs
I
OL
= 4 mA 0.4 V
V
OH(AJ)
High-level Annex J output voltage, CTL0,
CTL1, D0D7, C/LKON, SYSCLK outputs
Annex J: I
OH
= −9 mA,
ISO
= 0 V, V
DD
3 V
V
DD
−0.4 V
V
OL(AJ)
Low-level Annex J output voltage, CTL0,
CTL1, D0−D7, C/LKON, SYSCLK outputs
Annex J: I
OL
= 9 mA,
ISO
= 0 V, V
DD
3 V
0.4 V
I
(BH+)
Positive peak bus holder current, D0D7,
CTL0CTL1, LREQ
ISO = 3.6 V, V
DD
= 3.6 V,
V
I
= 0 V to V
DD
0.05 1 mA
I
(BH−)
Negative peak bus holder current,
D0D7, CTL0CTL1, LREQ
ISO = 3.6 V, V
DD
= 3.6 V,
V
I
= 0 V to V
DD
−1.0 −0.05 mA
I
I
Input current, LREQ, LPS, PD, TESTM,
SM, PC0PC2 inputs
ISO = 0 V, V
DD
= 3.6 V 5 µA
I
OZ
Off-state output current, CTL0, CTL1,
D0D7, C/LKON I/Os
V
O
= V
DD
or 0 V ±5 µA
I
(IRST)
Pullup current, RESET input V
I
= 1.5 V or 0 V −90 −20 µA
I
(SE_Pd)
Pulldown current, SE input V
I
= V
DD/2
or V
DD
5 50 µA
V
IT+
Positive input threshold voltage, LREQ,
CTL0, CTL1, D0D7 inputs
ISO = 0 V, V
DD
= 3V to 3.6 V V
DD
/2+0.3 V
DD
/2+0.9
V
IT+
Positive input threshold voltage, LPS
inputs
ISO = 0 V, V
DD
= 3 V to 3.6 V
V
ref
= 0.42 V
DD
V
REF
+1
V
V
IT
Negative input threshold voltage, LREQ,
CTL0, CTL1, D0D7 inputs
ISO= 0 V, V
DD
= 3 V to 3.6 V V
DD
/2−0.9 V
DD
/2−0.3
V
IT
Negative input threshold voltage, LPS
inputs
ISO= 0 V, V
ref
= 0.42 V
DD,
V
DD
= 3 V to 3.6 V
V
ref
+0.2
V
V
O
TPBIAS output voltage
At rated I
O
current 1.665 2.015 V
Measured at cable power side of resistor
TPBIAS is close to VDD when the port is not connected.
NOTES: 2. Transmit maximum packet (all ports transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous
interval, S400, data value of CCCCCCCCh), V
DD
= 3.3 V, T
A
= 25°C.
3. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and transmitting on the other port),
V
DD
= 3.3 V, T
A
= 25°C.
4. Idle (one port receiving and one port transmitting cycle starts), V
DD
= 3.3 V, T
A
= 25°C.