Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated
mode of operation (ISO
terminal is low) is as follows:
1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum
T
RESTORE
time, the LLC causes the interface to be initialized and restored to normal operation by
reactivating the LPS signal. In Figure 31 the interface is shown in the disabled state with SYSCLK
high-impedance inactive. However, the interface initialization sequence described here is also executed if
the interface is merely reset but not yet disabled.
2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that
LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3 ms for
SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. The PHY
commences SYSCLK activity by driving the SYSCLK output low for half a cycle. Thereafter, the SYSCLK
output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of 20.345 ns).
Upon the first full cycle of SYSCLK, the PHY drives the CTL and D terminals low for one cycle. The LLC
is also required to drive its CTL, D, and LREQ outputs low during one of the first six cycles of SYSCLK (this
is shown in Figure 31 as occurring in the first SYSCLK cycle).
3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the
receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles
(because the interface is in the differentiated mode of operation, the CTL and D lines are in the
high-impedance state after the first cycle).
4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This
indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The
PHY now accepts requests from the LLC via the LREQ line.
LPS
CTL0
LREQ
SYSCLK
D0−D7
CTL1
(1)
(2)
(3)
(4)
(high)
T
CLK_ACTIVE
7 Cycles
ISO
Figure 32. Interface Initialization, ISO High