Datasheet


   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for disabling the PHY-LLC interface when it is in the nondifferentiated mode of operation
(ISO
terminal is high) is as follows:
1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data
reception and transmission via the CTL and D lines, and request activity via the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface
bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.
3. Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any interface
bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.
4. Interface disabled. If the LPS signal remains inactive for T
LPS_DISABLE
time, the PHY terminates SYSCLK
activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state.
After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal
operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in Figure 31 and
Figure 32.
5 ns, Min
10 ns, Max
LPS
CTL0
LREQ
SYSCLK
D0−D7
CTL1
(1)
(2)
(3)
(4)
(low)
7 Cycles
T
CLK_ACTIVE
ISO
Figure 31. Interface Initialization, ISO Low