Datasheet


   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for disabling the PHY-LLC interface when it is in the differentiated mode of operation
(ISO
terminal is low) is as follows:
1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data
reception and transmission via the CTL and D lines, and request activity via the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface
bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should
terminate any output signal activity such that signals end in a logic 0 state).
3. Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any interface
bus activity, and places its CTL and D outputs into a high-impedance state (the PHY terminates any output
signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state.
4. Interface disabled. If the LPS signal remains inactive for T
LPS_DISABLE
time, the PHY terminates SYSCLK
activity by placing the SYSCLK output into a high-impedance state. The PHY-LLC interface is now in the
disabled state.
LPS
CTL0, CTL1
LREQ
SYSCLK
(3)
(2)
(1)
D0− D7
(high)
(4)
T
LPS_RESET
T
LPS_DISABLE
ISO
Figure 30. Interface Disable, ISO High