Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
interface reset and disable (continued)
Table 21. LPS Timing Parameters
PARAMETER DESCRIPTION MIN MAX UNIT
T
LPSL
LPS low time (when pulsed)
†
0.09 2.6 µs
T
LPSH
LPS high time (when pulsed)
†
0.021 2.6 µs
T
LPS_DUTY
LPS duty cycle (when pulsed)
‡
20% 55%
T
LPS_RESET
Time for PHY to recognize LPS deasserted and reset the interface 2.6 2.68 µs
T
LPS_DISABLE
Time for PHY to recognize LPS deasserted and disable the interface 26.03 26.11 µs
T
RESTORE
Time to permit optional isolation circuits to restore during an interface reset 15 23
§
µs
T
CLK_ACTIVATE
Time for SYSCLK to be activated from reassertion of LPS
PHY not in low-power state 60 ns
T
CLK_ACTIVATE
Time for SYSCLK to be activated from reassertion of LPS
PHY in low-power state 5.3 7.3 ms
†
The specified T
LPSL
and T
LPSH
times are worst-case values appropriate for operation with the TSB41AB1. These values are broader than those
specified for the same parameters in IEEE 1394a-2000 (that is, an implementation of LPS that meets the requirements of IEEE 1394a-2000
operates correctly with the TSB41AB1).
‡
A pulsed LPS signal must have a duty cycle (ratio of T
LPSH
to cycle period) in the specified range to ensure proper operation when using an
isolation barrier on the LPS signal (for example, as shown in Figure 14).
§
The maximum value for T
RESTORE
does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before
LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less
than T
LPS_DISABLE
.
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request
activity. When the PHY observes that LPS has been deasserted for T
LPS_RESET
, it resets the interface. When
the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity
on the LREQ signal. The timing for interface reset is shown in Figure 27 and Figure 28.
LPS
CTL0, CTL1
LREQ
SYSCLK
(3)
(2)
(1)
D0−D7
(low)
(4)
T
LPSH
T
LPS_RESET
T
RESTORE
T
LPSL
ISO
Figure 27. Interface Reset, ISO Low