Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
transmit (continued)
00
00 0000
(5)(4)(3)(2)(1)
01
0000
000011
D0–D7
CTL0, CTL1
SYSCLK
Link Controls CTL and D
PHY CTL and D Outputs are High Impedance
Figure 26. Cancelled/Null Packet Transmission Timing
The sequence of events for a cancelled/null packet transmission is as follows:
1. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the
interface to the link.
2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle
is optional; the link is not required to assert idle preceding hold.
3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold
cycle(s) are optional; the link is not required to assert hold preceding idle.
4. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle
on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may
assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert
hold. (It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold
cycles are asserted. This assures that either the link or PHY controls the interface in all cycles.)
5. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status
transfer, receive operation, or transmit operation.
interface reset and disable
The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a
reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface
is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any outstanding
bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status
information generated by the PHY is not queued, and thus does not cause a status transfer upon restoration
of the interface to normal operation.
The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface
is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY
and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be pulsed. In a direct
connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are
given in Table 21.