Datasheet


   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
receive (continued)
00
0010
00
01
XX
(1)
(2) (3)
FF (Data-On)
D0–D7
CTL0, CTL1
SYSCLK
Figure 24. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt a status
transfer operation that is in progress so that the CTL lines may change from status to receive without an
intervening idle.
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one cycle of idle following a receive operation.
transmit
When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.
If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the
grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then
takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless
the LLC is immediately releasing the interface, the LLC may assert idle for at most one clock before it must assert
either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while
it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the LLC need
not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time.
When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first
bits of packet data on the D lines. A transmit is held on the CTL terminals until the last bits of data have been
sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle
for one additional cycle before releasing the interface bus and placing its CTL and D terminals in
high-impedance. The PHY then regains control of the interface bus.
The hold asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another
packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request
by waiting the required minimum packet separation time and then asserting grant as before. This function may
be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets
during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during
a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet).
If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the
speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at
the end of a packet. The encoding for this speed code is the same as the speed code that precedes received
packet data as given in Table 20.