Datasheet


   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
output differentiation
The TSB41AB1 implements differentiation circuitry functionally equivalent to that shown in Figure 20 on the
bidirectional CTL0, CTL1, and D0–D7 terminals. The TSB41AB1 also implements an input hysteresis buffer
on the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also
implement similar output differentiation and input hysteresis circuitry on its CTL and D terminals and output
differentiation circuitry on its LREQ terminal.
DQ
DQ
DQ
3-State Output
Driver
Input Buffer With
Hysteresis
DIN
DOUT
ISO
OUTEN
INIT
SYSCLK
To/From
Internal
Device Logic
D Terminal
Figure 20. Input/Output Differentiation Logic
LLC service request
To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends
a serial bit stream on the LREQ terminal as shown in Figure 21.
LR(n-2)LR3LR2LR1LR0 LR(n-1)
NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.
Figure 21. LREQ Request Stream
The length of the stream varies depending on the type of request as shown in Table 12.
Table 12. Request Stream Bit Length
REQUEST TYPE NUMBER OF BITS
Bus request 7 or 8
Read register request 9
Write register request 17
Acceleration control request 6