Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
43
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
PHY-Link layer interface (continued)
The PHY may initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation whenever a packet is received from the serial bus.
The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.
The transmit operation is initiated when the PHY grants control of the interface to the LLC.
The encoding of the CTL0−CTL1 bus is shown in Table 10 and Table 11.
Table 10. CTL Encoding When PHY Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle No activity (this is the default mode)
0 1 Status Status information is being sent from the PHY to the LLC.
1 0 Receive An incoming packet is being sent from the PHY to the LLC.
1 1 Grant The LLC has been given control of the bus to send an outgoing packet.
Table 11. CTL Encoding When LLC Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle The LLC releases the bus (transmission has been completed).
0 1 Hold The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet
is to be transmitted (concatenated) without arbitrating.
1 0 Transmit An outgoing packet is being sent from the LLC to the PHY.
1 1 Reserved None
output differentiation
When an Annex J type isolation barrier is implemented between the PHY and LLC, the CTL0, CTL1, D0–D7,
and LREQ signals must be digitally differentiated so that the isolation circuits function correctly. Digital
differentiation is enabled on the TSB41AB1 when the ISO
terminal is low.
The differentiation operates such that the output is driven either low or high for one clock period whenever the
signal changes logic state, but otherwise places the output in a high-impedance state for as long as the signal
logic state remains constant. On input, hysteresis buffers are used to convert the signal to the correct logic state
when the signal is high impedance; the biasing network of the Annex J type isolation circuit pulls the signal
voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained.
The correspondence between the output logic state and the output signal level is shown in Figure 19.
011000100
LHZOZZHLZ
Logic State
Signal Level
Figure 19. Signal Transformation for Digital Differentiation