Datasheet

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   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRINCIPLES OF OPERATION
PHY-Link layer interface
The TSB41AB1 is designed to operate with an LLC such as the Texas Instruments TSB12LV21, TSB12LV22
TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. Details of operation for the
Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe
the operation of the PHY-LLC interface.
The interface to the LLC consists of the SYSCLK, CTL0, CTL1, D0–D7, LREQ, LPS, C/LKON, and ISO
terminals on the TSB41AB1, as shown in Figure 18.
Link
Layer
Controller
TSB41AB1
SYSCLK
CTL0−CTL1
D1−D7
LREQ
LPS
C/LKON
ISO
ISO ISO
Figure 18. PHY-LLC Interface
The SYSCLK terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to,
and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB41AB1 and LLC.
The D0–D7 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB41AB1 supports S100, S200, and S400 data transfers
over the D0–D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only
the D0–D3 terminals are used; and in S400 operation, all D0–D7 terminals are used for data transfer. When
the TSB41AB1 is in control of the D0–D7 bus, unused Dn terminals are driven low during S100 and S200
operations. When the LLC is in control of the D0–D7 bus, unused Dn terminals are ignored by the TSB41AB1.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.
The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SYSCLK.
The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC
either when LPS is inactive or when the PHY register LCtrl bit is zero.
The ISO
terminal is used to enable the output differentiation logic on the CTL0, CTL1 and D0–D7 terminals.
Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY and
LLC.
The TSB41AB1 normally controls the CTL0–CTL1 and D0–D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY
to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration.