Datasheet


   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
bus reset (continued)
The RHB and gap count may also be updated by PHY-config packets. The TSB41AB1 is IEEE 1394a-2000
compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and gap
count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received PHY-config
packets.
The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening write
to the gap count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a
PHY-config packet to be transmitted and then a bus reset initiated to verify that all nodes on the bus have
updated their RHBs and gap-count values, without having the gap count set back to 63 by the bus reset. The
subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap count of each
node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1
to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while the gap count of this
node remains set to the value just loaded by the write to PHY register 1.
Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the use
of the IBR bit, RHB, and gap count in PHY register 1:
D Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all
nodes have correctly updated their RHBs and gap-count values, and to ensure that a subsequent new
connection to the bus causes the gap count to be set to 63 on all nodes in the bus. If this bus reset is initiated
by setting the IBR bit to 1, the RHB and gap-count register must also be loaded with the correct values
consistent with the just transmitted PHY-config packet. In the TSB41AB1, the RHB and gap count have been
updated to their correct values upon the transmission of the PHY-config packet, and so these values may
first be read from register 1 and then rewritten.
D Other than to initiate the bus reset which must follow the transmission of a PHY-config packet, whenever
the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 to be
consistent with other nodes on the bus, and the RHB should be maintained with its current value.
D The PHY register 1 should not be written to except to set the IBR bit. The RHB and gap count should not
be written without also setting the IBR bit to 1.