Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
40
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
using the TSB41AB1 with a lower-speed link layer (continued)
In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node
(PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to
determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by sending
asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed map
may then be adjusted accordingly. The speed map should reflect that communication to such a node must be
done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed-map entries for
paths that merely pass through the node PHY, but do not terminate at that node, should not be restricted by the
lower speed of the LLC.
To assist in building an accurate speed map, the TSB41AB1 can indicate a speed capability other than S400
in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the vendor-dependent
page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID packet; it has no effect
on the speed signaled to peer PHYs during self-ID. The TSB41AB1 identifies itself as S400 capable to its peers
regardless of the value in the Link_Speed field.
Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is
determined that the speed map (if one exists) is incorrect for path entries terminating in the local node. If the
speed map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information
to build the speed map. In this case, the node may update the Link_Speed field to reflect the lower speed
capability of the LLC and then initiate another bus reset to cause the speed map to be rebuilt. Note that in this
scenario any speed-map entries for node-to-node communication paths that pass through the local node’s PHY
are restricted by the lower speed.
In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed
of the LLC without first checking the speed map. Changing the Link_Speed field in a leaf node can only affect
those paths that terminate at that node. Because no other paths can pass through a leaf node, it can have no
effect on other paths in the speed map. For hardware configurations, which can only be a leaf node (all ports
but one are unimplemented), it is recommended that the Link_Speed field be updated immediately after power
on or hardware reset.
power-up reset
To ensure proper operation of the TSB41AB1, the RESET terminal must be asserted low for a minimum of 2 ms
from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor
on the RESET
terminal to generate a power-on reset signal, the minimum reset time is assured if the capacitor
has a minimum value of 0.1 µF and also satisfies the following equation:
C
min
+ 0.0077 T ) 0.085
where C
min
is the minimum capacitance on the RESET terminal in µF, and T is the V
DD
ramp time, 10%–90%,
in milliseconds.
bus reset
In the TSB41AB1, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization
sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and gap-count register,
as required by IEEE 1394a-2000 (this configuration also maintains compatibility with older TI PHY designs
which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995). Therefore,
whenever the IBR bit is written, the RHB and gap count are also necessarily written.
(2)