Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
38
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POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
internal register configuration (continued)
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD SIZE TYPE DESCRIPTION
NPA 1 Rd/Wr Null-packet actions flag. This bit instructs the PHY not to clear fair and priority requests when a null packet
is received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared only when
a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and
malformed packets (less than 8 data bits) do not clear fair and priority requests. If 0, then fair and priority
requests are cleared when any non-ACK packet is received, including null packets or malformed packets
of less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus reset.
Link_Speed 2 Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code Speed
00 S100
01 S200
10 S400
11 illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY
and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer
PHYs during self-ID; the TSB41AB1 PHY identifies itself as S400 capable to its peers regardless of the
value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus reset.
SWR 1 Rd/Wr Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (just as momentarily asserting
the RESET terminal low). This bit is always read as a 0.
power-class programming
The PC0–PC2 terminals are programmed to set the default value of the power class indicated in the pwr field
(bits 21–23) of the transmitted self-ID packet. Descriptions of the various power classes are given in Table 9.
The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently
loaded into the Pwr_Class field in register 4.
Table 9. Power Class Descriptions
PC0−PC2 DESCRIPTION
000 Node does not need power and does not repeat power.
001 Node is self-powered and provides a minimum of 15 W to the bus.
010 Node is self-powered and provides a minimum of 30 W to the bus.
011 Node is self-powered and provides a minimum of 45 W to the bus.
100 Node may be powered from the bus for the PHY only using up to 3 W and may also provide power to the bus. The amount of
bus power that it provides can be found in the configuration ROM.
101 Reserved
110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.