Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
32
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APPLICATION INFORMATION
designing with the PowerPad package (continued)
Other requirements for thermal lands and thermal vias are detailed in the PowerPAD Thermally Enhanced
Package technical brief, TI literature number SLMA002, available via the TI Web pages beginning at URL
http://www.ti.com
.
Figure 17. Example of a Thermal Land for the TSB41AB1PAP PHY
For the TSB41AB1, this thermal land should be grounded to the low-impedance ground plane of the device.
This improves not only thermal performance but also the electrical grounding of the device. It is also
recommended that the device ground terminal landing pads be connected directly to the grounded thermal land.
The land size should be as large as possible without shorting device signal terminals. The thermal land may
be soldered to the exposed PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is
recommended that the thermal land be connected to the low-impedance ground plane for the device. More
information may be obtained from the TI application report Recommendations for PHY Layout, TI literature
number SLLA020.
internal register configuration
There are 16 accessible internal registers in the TSB41AB1. The configuration of the registers at addresses 0h
through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected. The
selected page is set in base register 7.
The configuration of the base registers is shown in Table 1, and corresponding field descriptions are given in
Table 2. The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as Reserved or Rsvd in register configuration tables) is read as 0,
but is subject to future usage. All registers in pages 2 through 6 are reserved.
Table 1. Base Register Configuration
ADDRESS BIT POSITION
0 1 2 3 4 5 6 7
0000 Physical ID R CPS
0001 RHB IBR Gap_Count
0010 Extended (111b) Num_Ports (00001b)
0011 PHY_Speed (010b) Rsvd Delay (0000b)
0100 LCtrl C Jitter (000b) Pwr_Class
0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC
0110 Reserved
0111 Page_Select Rsvd Port_Select