Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted) (continued)
device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
See Note 2 48
I
DD
Supply current
See Note 3 42
mA
I
DD
Supply current
See Note 4 41
mA
I
DD(ULP)
Supply current, ultralow-power mode
V
DD
= 3.3 V, T
A
= 25°C,
Port disabled or unconnected,
PD = 0 V, LPS = 0 V
150 µA
I
DD(PD)
Supply current, power-down mode
PD = V
DD
, V
DD
= 3.3 V,
T
A
= 25°C
150 µA
V
(TH)
Power status threshold, CPS input
†
400-kΩ resistor
†
4.7 7.5 V
V
OH
High-level output voltage, CTL0, CTL1,
V
DD
= 2.7 V, I
OH
= −4 mA 2.2
V
V
OH
High-level output voltage, CTL0, CTL1,
D0−D7, CNA, C/LKON, SYSCLK outputs
V
DD
= 3 to 3.6 V, I
OH
= −4 mA 2.8
V
V
OL
Low-level output voltage, CTL0, CTL1,
D0−D7, CNA, C/LKON, SYSCLK outputs
I
OL
= 4 mA 0.4 V
V
OH(AJ)
High-level Annex J output voltage, CTL0,
CTL1, D0−D7, C/LKON, SYSCLK outputs
Annex J: I
OH
= −9 mA,
ISO
= 0 V, V
DD
≥ 3 V
V
DD
−0.4 V
V
OL(AJ)
Low-level Annex J output voltage, CTL0,
CTL1, D0−D7, C/LKON, SYSCLK outputs
Annex J: I
OL
= 9 mA,
ISO
= 0 V, V
DD
≥ 3 V
0.4 V
I
(BH+)
Positive peak bus holder current, D0−D7,
CTL0, CTL1, LREQ
ISO = 3.6 V, V
DD
= 3.6 V,
V
I
= 0 V to V
DD
0.05 1 mA
I
(BH−)
Negative peak bus holder current,
D0−D7, CTL0, CTL1, LREQ
ISO = 3.6 V, V
DD
= 3.6 V,
V
I
= 0 V to V
DD
−1.0 −0.05 mA
I
I
Input current, LREQ, LPS, PD, TESTM,
SM, PC0–PC2 inputs
ISO = 0 V, V
DD
= 3.6 V 5 µA
I
OZ
Off-state output current, CTL0, CTL1,
D0–D7, C/LKON I/Os
V
O
= V
DD
or 0 V ±5 µA
I
(IRST)
Pullup current, RESET input V
I
= 1.5 V or 0 V −90 −20 µA
I
(SE−Pd)
Pullup/pulldown current, SE input V
I
= V
DD/2
or V
DD
5 50 µA
V
IT+
Positive input threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
‡
ISO = 0 V, V
DD
= 3 V to 3.6 V V
DD
/2+0.3 V
DD
/2+0.9
V
V
IT+
Positive input threshold voltage, LPS
inputs
ISO = 0 V, V
DD
= 3 V to 3.6 V
V
ref
= 0.4 V
DD
V
REF
+1
V
V
IT−
Negative input threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
‡
ISO= 0 V, V
DD
= 3 V to 3.6 V V
DD
/2−0.9 V
DD
/2−0.3
V
V
IT−
Negative input threshold voltage, LPS
inputs
ISO= 0 V, V
ref
= 0.4 V
DD
,
V
DD
= 3 V to 3.6 V
V
ref
+0.2
V
V
O
TPBIAS output voltage
§
At rated I
O
current 1.665 2.015 V
†
Measured at cable power side of resistor
‡
This parameter applicable only when ISO
low
§
TPBIAS is typically V
DD
−0.2 V when the port is not connected.
NOTES: 2. Transmit maximum packet (one port transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous
interval, S400, data value of CCCCCCCCh), V
DD
= 3.3 V, T
A
= 25°C.
3. Receive typical packet (one port receiving DV packets on every isochronous interval, S100), V
DD
= 3.3 V, T
A
= 25°C.
4. Idle (one port transmitting cycle starts), V
DD
= 3.3 V, T
A
= 25°C.