Datasheet

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   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
TERMINAL
NAME
NUMBER
TYPE I/O DESCRIPTION
NAME
PAP
PHP GQE/ZQE
TYPE
I/O
DESCRIPTION
RESET 53 37 A8 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal
pullup resistor to V
DD
is provided so only an external delay capacitor is required for
proper power-up operation (see power-up reset in the Application Information
section). The RESET
terminal also incorporates an internal pulldown which is
activated when the PD input is asserted high. This input is otherwise a standard logic
input, and may also be driven by an open-drain type driver.
SE 28 23 H6 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal may be tied to GND through a 1-kΩ pulldown resistor or it
may be tied to GND directly.
SM 29 24 J7 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to GND.
SYSCLK 2 1 A1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data
transfers, to the LLC.
TESTM 27 22 J6 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal, use this terminal should be tied to V
DD
through a 1-kΩ resistor.
TPA+ 37 30 F9 Cable I/O
Twisted-pair cable A differential signal terminals. Board traces from the pair o
f
positive and negative differential signal terminals should be kept matched and as
TPA− 36 29 G9 Cable I/O
positive and negative differential signal terminals should be kept matched and as
short as possible to the external load resistors and to the cable connector.
TPB+ 35 28 H9 Cable I/O
Twisted-pair cable B differential signal terminals. Board traces from the pair o
f
positive and negative differential signal terminals should be kept matched and as
TPB− 34 27 J9 Cable I/O
positive and negative differential signal terminals should be kept matched and as
short as possible to the external load resistors and to the cable connector.
TPBIAS 38 31 E9 Cable I/O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for
proper operation of the twisted-pair cable drivers and receivers, and for signaling to
the remote nodes that there is an active cable connection.
XI
XO
59
60
42
43
A5
A4
Crystal − Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant
fundamental mode crystal. The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used (see crystal selection in the
Application Information section). When an external clock source is used, XI should
be the input and XO should be left open, and the clock must be supplied before the
device is taken out of reset.
NOTE: It is strongly recommended that signals tied to V
DD
use a 1-kΩ resistor (minimum). Tying signals directly to V
CC
may result in ESD failures.
Signals tied to ground may be tied directly.