Datasheet
SLLS423I − JUNE 2000 − REVISED MARCH 2005
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
TERMINAL
NAME
NUMBER
TYPE I/O DESCRIPTION
NAME
PAP
PHP GQE/ZQE
TYPE
I/O
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
6
7
8
9
10
11
12
13
4
5
6
7
8
9
10
11
C1
D2
D1
E2
E1
F1
F2
G1
CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the
LLC. Bus holders are built into these terminals.
DGND 17, 18,
63, 64
14, 46,
47
B3, H2 Supply − Digital circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
DV
DD
25, 26,
61, 62
21, 44,
45
A3, H5 Supply − Digital circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 µF and
0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended.
These supply terminals are separated from PLLV
DD
and AV
DD
inside the
device to provide noise isolation. They should be tied at a low-impedance point
on the circuit board.
FILTER0
FILTER1
54
55
38
39
B7
A7
CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to
form a lag-lead filter required for stable operation of the internal frequency
multiplier PLL running from the crystal oscillator. A 0.1-µF ±10% capacitor is
the only external component required to complete this filter.
ISO 23 19 H4 CMOS I Link interface isolation control input. This terminal controls the operation of
output differentiation logic on the CTL and D terminals. If an optional Annex J
type isolation barrier is implemented between the TSB41AB1 and LLC, the ISO
terminal should be tied low to enable the differentiation logic. If no isolation
barrier is implemented (direct connection), or TI bus holder isolation is
implemented, the ISO
terminal should be tied high through a pullup to disable
the differentiation logic. For additional information see the TI application note
Galvanic Isolation of the IEEE 1394-1995 Serial Bus, literature number
SLLA011.
LPS 15 13 H1 CMOS I Link power status input. This terminal monitors the active/power status of the
link layer controller and controls the state of the PHY-LLC interface. This
terminal should be connected through a 10-kΩ resistor either to the V
DD
supplying the LLC, or to a pulsed output which is active when the LLC is
powered (see Figure 13). A pulsed signal should be used when an isolation
barrier exists between the LLC and PHY (see Figure 14).
The LPS input is considered inactive if it is sampled low by the PHY for more
than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (that is,
asserted steady high or an oscillating signal with a low time less than 2.6 µs).
The LPS input must be high for at least 21 ns to assure that a high is observed
by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC
interface into a low-power reset state. In the reset state, the CTL and D outputs
are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than
26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The PHY-LLC
interface is placed into the disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is
inactive or the LCtrl register bit is cleared to 0.
LREQ 1 48 A2 CMOS I LLC request input. The LLC uses this input to initiate a service request to the
TSB41AB1. Bus holder is built into this terminal.