Datasheet


   

SLLS423I − JUNE 2000 − REVISED MARCH 2005
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
functional block diagram
Received Data
Decoder/Retimer
Link
Interface
I/O
Arbitration
and Control
State Machine
Logic
Bias Voltage
and
Current
Generator
Transmit Data
Encoder
Cable Port
Crystal
Oscillator,
PLL System,
and Clock
Generator
TPA+
CPS
TPA−
TPB+
TPB−
XI
XO
FILTER0
FILTER1
LPS
ISO
CNA
†
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
C/LKON
R0
R1
TPBIAS
PD
RESET
†
CNA output is only available in the 64-pin PAP package