Datasheet

TSB12LV32/Phy Interface
91
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
8.6 TSB12LV32/Phy Interface Critical Timing
SCLK
LREQ
CYCLEIN
CONTNDR
CTL[0:1]
D[0:7]
X X
XX XX
t
d0
t
d2
t
d1
CONTROL
DATADATA
CONTROL
t
su3
t
su2
t
su0
t
su1
t
h3
t
h2
t
h1
t
h0
Figure 8−7. Critical Timing for the TSB12LV32/Phy Interface
Table 8−12. TSB12LV32/Phy Interface Timing
PARAMETER
†
TERMINAL NAME MIN MAX UNIT
t
d0
LREQ 3 9.5 ns
t
d1
Delay time (SCLK to Q)
CTL[0:1] 3 9.5 ns
t
d2
Delay time (SCLK to Q)
D[0:7] 3.5 9 ns
t
su0
CYCLEIN 2 ns
t
su1
Setup time to SCLK
CONTNDR 3 ns
t
su2
Setup time to SCLK
CTL[0:1] 3 ns
t
su3
D[0:7] 3 ns
t
h0
CYCLEIN 2 ns
t
h1
Hold time from SCLK
CONTNDR 2 ns
t
h2
Hold time from SCLK
CTL[0:1] 0 ns
t
h3
D[0:7] 0 ns
†
All timing parameters are referenced to the rising edge of SCLK on the TSB12LV32 side.