Datasheet

TSB12LV32/Phy Interface

SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP

The hold state asserted at the end of packet transmission indicates to the Phy that the TSB12LV32 requests

to send another packet (concatenated packet) without releasing the serial bus. The Phy responds to this

concatenation request by waiting the required minimum packet separation time and then asserting grant as

before. This function can be used to send a unified response after sending an acknowledge, or to send

consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is

enabled, all packets transmitted during a single bus ownership must be of the same speed (because the speed

of the packets is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of

Phy register 5 is set), the TSB12LV32 must specify the speed code of the next concatenated packet on the

D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code

is the same as the speed code that precedes received packet data as given in Table 8−11.

After sending the last packet for the current bus ownership, the TSB12LV32 releases the bus by asserting idle

on the CTL terminals for two clock cycles. The Phy begins asserting idle on the CTL terminals one clock after

sampling idle from the link. Note that whenever the D and CTL terminals change direction between the Phy

and the TSB12LV32, there is an extra clock period allowed so that both sides of the interface can operate on

registered versions of the interface signals.

00 0000

(f)

(g)(e)(d)(c)(b)(a)

SPD

0000

000011

dnd0

Link Controls CTL and D

Phy CTL and D Outputs Are High Impedance

D[0:7]

CTL[0:1]

SYSCLK

NOTE: SPD = Speed code, see Table 8−11, d0–dn = Packet data

Figure 8−6. Normal Packet Transmission Timing

The sequence of events for a normal packet transmission is as follows:

• Transmit operation initiated. The Phy asserts grant on the CTL lines followed by idle to hand over control

of the interface to the link so that the link can transmit a packet. The Phy releases control of the interface

(i.e., it places its CTL and D outputs in a high-impedance state) following the idle cycle.

• Optional idle cycle. The link can assert at most one idle cycle preceding assertion of either hold or transmit.

This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

• Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of transmit. These

hold cycle(s) are optional; the link is not required to assert hold preceding transmit.