Datasheet

TSB12LV32/Phy Interface
89
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
• Receive data. Following the data-on indication (if any) and the speed-code, the Phy asserts packet data
on the D lines with receive on the CTL lines for the remainder of the receive operation.
• Receive operation terminated. The Phy terminates the receive operation by asserting idle on the CTL
lines. The Phy asserts at least one cycle of idle following a receive operation.
00
0010
00
01
XX dnd0SPD
(a)
(e)(d)(b) (c)
FF (Data-On)D[0:7]
CTL[0:1]
SYSCLK
Figure 8−5. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
• Receive operation initiated. The Phy indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a
status transfer operation that is in progress so that the CTL lines can change from status to receive without
an intervening idle.
• Data-on indication. The Phy asserts the data-on indication code on the D lines for one or more cycles.
• Receive operation terminated. The Phy terminates the receive operation by asserting idle on the CTL
lines. The Phy asserts at least one cycle of idle following a receive operation.
Table 8−11. Receive Speed Codes
D0−D7 DATA RATE
00XX XXXX S100
0100 XXXX S200
0101 0000 S400
1YYY YYYY Data-on indication
NOTE: X = Output as 0 by Phy, ignored by TSB12LV32
Y = Output as 1 by Phy, ignored by TSB12LV3
8.5 Transmit Operation
When the TSB12LV32 issues a bus request through the LREQ terminal, the Phy arbitrates to gain control of
the bus. If the Phy wins arbitration for the serial bus, the Phy-LLC interface bus is granted to the TSB12LV32
by asserting the grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock
cycle. The TSB12LV32 then takes control of the bus by asserting either idle (00b), hold (01b), or transmit (10b)
on the CTL terminals. Unless the TSB12LV32 immediately releases the interface, the TSB12LV32 can assert
the idle state for at most one clock before it must assert either hold or transmit on the CTL terminals. The hold
state is used by the TSB12LV32 to retain control of the bus while it prepares data for transmission. The
TSB12LV32 can assert hold for zero or more clock cycles (i.e., the TSB12LV32 need not assert hold before
transmit). The Phy asserts data-prefix on the serial bus during this time.
When the TSB12LV32 is ready to send data, the TSB12LV32 asserts transmit on the CTL terminals as well
as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the
last bits of data have been sent. The TSB12LV32 then asserts either hold or idle on the CTL terminals for one
clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and placing its
CTL and D terminals in high impedance. The Phy then regains control of the interface bus.