Datasheet

TSB12LV32/Phy Interface
88
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
The sequence of events for a status transfer is as follows:
• Status transfer initiated. The Phy indicates a status transfer by asserting status on the CTL lines along
with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless
interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer
occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data
is to be sent in addition to any status information.
• Status transfer terminated. The Phy normally terminates a status transfer by asserting idle on the CTL
lines. The Phy can also interrupt a status transfer at any cycle by asserting receive on the CTL lines to
begin a receive operation. The Phy shall assert at least one cycle of idle between consecutive status
transfers.
8.4 Receive Operation
Whenever the Phy detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The Phy indicates
the start of a packet by placing the speed code (encoded as shown in Table 8−11 on the D terminals, followed
by packet data. The Phy holds the CTL terminals in the receive state until the last symbol of the packet has
been transferred. The Phy indicates the end of packet data by asserting idle on the CTL terminals. All received
packets are transferred to the TSB12LV32. Note that the speed code is part of the Phy-LLC protocol and is
not included in the calculation of CRC or any other data protection mechanisms.
It is possible for the Phy to receive a null packet, which consists of the data-prefix state on the serial bus
followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet
speed exceeds the capability of the receiving Phy, or whenever the TSB12LV32 immediately releases the bus
without transmitting any data. In this case, the Phy asserts receive on the CTL terminals with the data-on
indication (all 1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data
being transferred. In all cases, the TSB41LV03A sends at least one data-on indication before sending the
speed code or terminating the receive operation.
The TSB41LV03A also transfers its own self-ID packet, transmitted during the self-ID phase of bus
initialization, to the TSB12LV32. This packet is transferred to the TSB12LV32 just as any other received self-ID
packet.
00
0010
00
01
XX dnd0SPD
(a)
(e)(d)(b) (c)
FF (Data-On)D[0:7]
CTL[0:1]
SYSCLK
Figure 8−4. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:
• Receive operation initiated. The Phy indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a
status transfer operation that is in progress so that the CTL lines can change from status to receive without
an intervening idle.
• Data-on indication. The Phy asserts the data-on indication code on the D lines for one or more cycles
preceding the speed-code.
• Speed-code. The Phy indicates the speed of the received packet by asserting a speed-code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive
cycle for which the D lines are not the data-on code. If the speed-code is invalid, or indicates a speed higher
than that which the link is capable of handling, the link ignores the subsequent data.