Datasheet

TSB12LV32/Phy Interface
87
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit
the cycle start message under certain circumstances. The acceleration control request is therefore provided
to allow the TSB12LV32 to temporarily enable or disable the arbitration acceleration enhancements of the
TSB41LV03A during the asynchronous period. The TSB12LV32 typically disables the enhancements when
its internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables the
enhancements when it receives a cycle start message. The acceleration control request can be made at any
time, however, and is immediately serviced by the Phy. Additionally, a bus reset or isochronous bus request
causes the enhancements to be re-enabled, if the EAA bit is set.
8.3 Status Transfer
A status transfer is initiated by the Phy when there is status information to be transferred to the TSB12LV32.
The Phy waits until the interface is idle before starting the transfer. The transfer is initiated by the Phy asserting
status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals.
The Phy maintains CTL = status for the duration of the status transfer. The Phy can prematurely end a status
transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received
before the status transfer completes. The Phy continues to attempt to complete the transfer until all status
information has been successfully transmitted. There is at least one idle cycle between consecutive status
transfers.
The Phy normally sends just the first four bits of status to the TSB12LV32. These bits are status flags that are
needed by the TSB12LV32 state machines. The Phy sends an entire 16-bit status packet to the TSB12LV32
after a read register request, or when the Phy has pertinent information to send to the TSB12LV32 or
transaction layers. The only defined condition where the Phy automatically sends a register to the TSB12LV32
is after self-ID, when the Phy sends the physical-ID register that contains the new node address. All status
transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to
have been successfully transmitted to the TSB12LV32 immediately upon being sent, even if a received packet
subsequently interrupts the status transfer. Register contents are considered to have been successfully
transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted
only if any status flags remain to be sent, or if a register transfer has not yet completed.
The definition of the bits in the status transfer are shown in Table 8−10 and the timing is shown in Figure 8−3.
Table 8−10. Status Bits
BIT(S) NAME DESCRIPTION
0 Arbitration reset gap Indicates that the Phy has detected that the bus has been idle for an arbitration reset gap time (as defined in
IEEE Std 1394−1995). This bit is used by the TSB12LV32 in the busy/retry state machine.
1 Subaction gap Indicates that the Phy has detected that the bus has been idle for a subaction gap time (as defined in IEEE
Std 1394−1995). This bit is used by the TSB12LV32 to detect the completion of an isochronous cycle.
2 Bus reset Indicates that the Phy has entered the start of the bus reset state.
3 Interrupt Indicates that a Phy interrupt event has occurred. An interrupt event can be a configuration time-out,
cable-power voltage falling too low, a state time-out, or a port status change.
4−7 Address This field holds the address of the Phy register whose contents are being transferred to the TSB12LV32.
8−15 Data This field holds the register contents.
00
00
(a)
01
(b)
00
00 S[14:15]S[0:1]D[0:1]
CTL[0:1]
SYSCLK
Figure 8−3. Status Transfer Timing