Datasheet

TSB12LV32/Phy Interface
86
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 8−8.
Table 8−8. Write Register Request
BIT(S) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1−3 Request type A 101 indicating this is a write register request
4−7 Address Identifies the address of the Phy register to be written to
8−15 Data Gives the data that is to be written to the specified register address
16 Stop bit Indicates the end of the transfer (always 0)
For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 8−9.
Table 8−9. Acceleration Control Request
BIT(S) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1−3 Request type A 110 indicating this is a acceleration control request
4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0.
5 StopbBit Indicates the end of the transfer (always 0)
For fair or priority access, the TSB12LV32 sends the bus request (FairReq or PriReq) at least one clock after
the Phy-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the Phy,
then any pending fair or priority request is lost (cleared). Additionally, the Phy ignores any fair or priority
requests if the receive state is asserted while the TSB12LV32 is sending the request. The TSB12LV32 can
then reissue the request one clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or
transmitting a cycle start message, the TSB12LV32 can issue an isochronous bus request (IsoReq). The Phy
clears an isochronous request only when the serial bus has been won.
To send an acknowledge packet, the TSB12LV32 must issue an immediate bus request (ImmReq) during the
reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of
the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends,
the Phy immediately grants control of the bus to the TSB12LV32. The TSB12LV32 sends an acknowledgment
to the sender unless the header CRC of the received packet is corrupted. In this case, the TSB12LV32 does
not transmit an acknowledge, but instead cancels the transmit operation and releases the interface
immediately; the TSB12LV32 must not use this grant to send another type of packet. After the interface is
released the TSB12LV32 can proceed with another request.
The TSB12LV32 can make only one bus request at a time. Once the TSB12LV32 issues any request for bus
access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the Phy indicates that
the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and
the TSB12LV32 granted control). The Phy ignores new bus requests while a previous bus request is pending.
All bus requests are cleared upon a bus reset.
For write register requests, the Phy loads the specified data into the addressed register as soon as the request
transfer is complete. For read register requests, the Phy returns the contents of the addressed register to the
TSB12LV32 at the next opportunity through a status transfer. If a received packet interrupts the status transfer,
then the Phy continues to attempt the transfer of the requested register until it is successful. A write or read
register request can be made at any time, including while a bus request is pending. Once a read register
request is made, the Phy ignores further read register requests until the register contents are successfully
transferred to the TSB12LV32. A bus reset does not clear a pending read register request.
The TSB41LV03A includes several arbitration acceleration enhancements, which allow the Phy to improve
bus performance and throughput by reducing the number and length of interpacket gaps. These
enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority
packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration
following acknowledge packets. The enhancements are enabled when the EAA bit in Phy register 5 is set.