Datasheet

TSB12LV32/Phy Interface

SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP

Table 8−3. Request Stream Bit Length

REQUEST TYPE NUMBER OF BITS

Bus request 7 or 8

Read register request 9

Write register request

Acceleration control request 6

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of

0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type

of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit

stream. The LREQ terminal is normally low.

Encoding for the request type is shown in Table 8−4.

Table 8−4. Request Type Encoding

LR1–LR3 NAME DESCRIPTION

000 ImmReq Immediate bus request. Upon detection of idle, the Phy takes control of the bus immediately without arbitration.

001 IsoReq Isochronous bus request. Upon detection of idle, the Phy arbitrates for the bus without waiting for a subaction gap.

010 PriReq Priority bus request. The Phy arbitrates for the bus after a subaction gap, ignores the fair protocol.

011 FairReq Fair bus request. The Phy arbitrates for the bus after a subaction gap, follows the fair protocol.

100 RdReg The Phy returns the specified register contents through a status transfer.

101 WrReg Write to the specified register

110 AccelCtl Enable or disable asynchronous arbitration acceleration

111 Reserved Reserved

For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 8−5.

Table 8−5. Bus Request

BIT(S) NAME DESCRIPTION

0 Start bit Indicates the beginning of the transfer (always 1)

1−3 Request type Indicates the type of bus request (see Table 8−4)

4−6 Request speed Indicates the speed at which the Phy sends the data for this request (see Table 8−6) for the encoding of this field.

7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, this bit can be omitted.

The 3-bit request speed field used in bus requests is shown in Table 8−6.

Table 8−6. Bus Request Speed Encoding

LR4–LR6 DATA RATE

000 S100

010 S200

100 S400

All others Invalid

NOTE: The TSB41LV03A accepts a bus request with an invalid speed code and process the

bus request normally. However, during packet transmission for such a request, the

TSB41LV03A ignores any data presented by the TSB12LV32 and transmits a null packet.

For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 8−7.