Datasheet

TSB12LV32/Phy Interface

SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP

The LREQ terminal is controlled by the TSB12LV32 to send serial service requests to the Phy in order to

request access to the serial bus for packet transmission, read or write Phy registers, or control arbitration

acceleration.

The LPS and LINKON terminals are used for power management of the Phy and TSB12LV32. The LPS

terminal indicates the power status of the TSB12LV32, and can be used to reset the Phy-LLC interface or to

disable SYSCLK. The C/LKON terminal is used to send a wake-up notification to the TSB12LV32 and to

indicate an interrupt to the TSB12LV32 when either LPS is inactive or the Phy register LCtrl bit is zero.

The TSB41LV03A normally controls the CTL0–CTL1 and D0–D7 bidirectional buses. The TSB12LV32 is

allowed to drive these buses only after the TSB12LV32 has been granted permission to do so by the Phy.

There are four operations that can occur on the Phy-LLC interface: link service request, status transfer, data

transmit, and data receive. The TSB12LV32 issues a service request to read or write a Phy register, to request

the Phy to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration.

The Phy can initiate a status transfer either autonomously or in response to a register read request from the

TSB12LV32. The Phy initiates a receive operation whenever a packet is received from the serial bus. The Phy

initiates a transmit operation after winning control of the serial bus following a bus request by the TSB12LV32.

The transmit operation is initiated when the Phy grants control of the interface to the TSB12LV32.

The encoding of the CTL0−CTL1 bus is shown in Table 8−1 and Table 8−2.

Table 8−1. CTL Encoding When the Phy Has Control of the Bus

CTL0 CTL1 NAME DESCRIPTION

0 0 Idle No activity (this is the default mode)

0 1 Status Status information is being sent from the Phy to the TSB12LV32.

1 0 Receive An incoming packet is being sent from the Phy to the TSB12LV32.

1 1 Grant The TSB12LV32 has been given control of the bus to send an outgoing packet.

Table 8−2. CTL Encoding When the TSB12LV32 Has Control of the Bus

CTL0 CTL1 NAME DESCRIPTION

0 0 Idle The TSB12LV32 releases the bus (transmission has been completed).

0 1 Hold The TSB12LV32 is holding the bus while data is being prepared for transmission, or indicating that another

packet is to be transmitted (concatenated) without arbitrating.

1 0 Transmit An outgoing packet is being sent from the TSB12LV32 to the Phy.

1 1 Reserved Reserved

8.2 TSB12LV32 Service Request

To request access to the bus, to read or write a Phy register, or to control arbitration acceleration, the

TSB12LV32 sends a serial bit stream on the LREQ terminal as shown in Figure 8−2.

……

LR0 LR1 LR2

LR(n−2)

LR3

LR(n−1)

NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.

Figure 8−2. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in Table 8−3.