Datasheet

TSB12LV32/Phy Interface
83
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
8 TSB12LV32/Phy Interface
This section provides an overview of the digital interface between a TSB12LV32 and a physical layer device
(Phy). The information that follows can be used as a guide through the process of connecting the TSB12LV32
to a 1394 Phy. The part numbers referenced, the TSB41LV03A and the TSB12LV32, represent the Texas
Instruments implementation of the Phy (TSB41LV03A) and link (TSB12LV32) layers of the IEEE 1394-1995
and 1394a-2000 standards.
The specific details of how the TSB41LV03A device operates are not discussed in this document. Only those
parts that relate to the TSB12LV32 Phy interface are mentioned.
8.1 Principles of Operation
The TSB12LV32 is designed to operate with a Texas Instruments physical-layer device. The following
paragraphs describe the operation of the Phy-LLC interface assuming a TSB41LV03A Phy. The TSB41LV03A
is an IEEE 1394a-2000 three-port cable transceiver/arbiter Phy capable of 400-Mbps speeds.
The interface to the Phy consists of the SCLK, CTL0–CTL1, D0–D7, LREQ, LPS, LINKON, and DIRECT
terminals on the TSB12LV32, as shown in Figure 8−1. See TSB12LV32 (GP2Lynx)/TSB41LV03 Reference
Schematic application report, Texas Instruments literature number SLLA044, for a detailed description of the
electrical interface between the TSB12LV32 and TSB41LV03.
TSB12LV32
DIRECT
LINKON
LPS
SCLK
LREQ
D[0:7]
CTL[0:1]
Link-Layer
Controller
TSB41LV03A
ISO
C/LKON
LPS
SYSCLK
LREQ
D[0:7]
CTL[0:1]
Physical-Layer
Device
ISODIRECT
Phy-LLC Interface
Figure 8−1. Phy-LLC Interface
The SYSCLK from the Phy terminal provides a 49.152-MHz interface clock. All control and data signals are
synchronized to, and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB41LV03A and TSB12LV32.
The D0–D7 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB41LV03A supports S100, S200, and S400 data
transfers over the D0–D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200
operation only the D0–D3 terminals are used; and in S400 operation all D0–D7 terminals are used for data
transfer. When the TSB41LV03A is in control of the D0–D7 bus, unused Dn terminals are driven low during
S100 and S200 operations. When the TSB12LV32 is in control of the D0–D7 bus, unused Dn terminals are
ignored by the TSB41LV03A.