Datasheet

FIFO Memory Access

SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP

To perform a burst write operation, the microcontroller must continually drive MCS low. The TSB12LV32 loads

MD0–MD15 to the ATF during each rising edge of BCLK while MCS

is low. At the same time it asserts MCA

(MCA is always one cycle behind MCS) low.

The ATF_First_Update address location is optimized for transmitting zero-length isochronous packets or

asynchronous stream packets. A zero-length packet contains no data payload and only the packet header and

header CRC are transmitted.

6.4 General-Receive FIFO (GRF)

The GRF contains a 520 quadlet RAM, a prefetch buffer and control logic. When the recevied paacket has

been verified and the GRF RAM has enough space to hold the whole packet (CRCs not included), the

hardware triggers a receive packet interrupt, RXGRFPKT, in the interrupt register at 0Ch and the GRF prefetch

buffer automatically reads the data from the RAM. The GRF prefetch buffer is used to support the

microinterface burst read operation. Microcontroller read access to the GRF is performed by a read from the

address location 60h, GRF Data.

The GRF accumulates self-ID packets upon 1394 bus reset. All quadlets of a self-ID packet are saved in the

GRF after power up. TSB12LV32 hardware checks to ensure that the second quadlet is indeed the

complement (logical inverse) of the first quadlet of the self-ID. If there are any errors associated with the self-ID

process, a self-ID interrupt, SELFIDER, is generated in the interrupt register at 0Ch and the self-ID error code

field, SIDERCODE, at 08h is updated to reflect the error(s). The option to check for the logical inverse of the

self-ID in the second quadlet can be turned off by setting to 0 the FULLSID bit in the control register at 08h.

6.5 GRF Stored Data Format

Each quadlet in the GRF is internally 33 bits wide. The most significant bit (extra bit) is used to indicate whether

it is a packet token or a regular received quadlet (received header CRC and data CRC are checked and not

stored in GRF). This bit is called the CD bit, which value is reflected in bit 6 of the FIFO status register. If the

CD bit is 1, the next quadlet read from the GRF is a packet token. If the CD bit is 0, the next quadlet read from

the GRF is a regular received quadlet. A packet token is stored as the first quadlet for each received confirmed

packet. The definition for a packet token is shown in Table 6−1. Bit 0 is most significant bit and bit 32 is the

least significant bit.

Table 6−1. Packet Token Definition

BITS NAME DESCRIPTION

0 CD CD bit is 1 for packet token. This bit should only be read from the FIFO status register at 30h.

1−2 RESERVED Reserved

3−16 QUADLET_COUNT Expected quadlet count after packet token for this received packet

17−19 RESERVED Reserved

20−24 ackCode If bit 20 is 0, bits[21:24] are used as the Ack code that is sent back to the transmitting node. If bit 20 is 1, it is an

error condition and an error Ack code is sent to the transmitting node.

25−26 RESERVED Reserved

27−28 SPEED The speed code for the received packet.

00 – 100 Mbps

01 – 200 Mbps

10 – 400 Mbps

29−32 RESERVED Reserved