Datasheet

FIFO Memory Access
66
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
Each quadlet can be written into the ATF register on a byte (8-bit) boundary or word (16-bit) boundary. To write
to the ATF in a byte fashion, the following steps should be followed.
Step 1: Writing the first quadlet of the packet:
a) Write the first 8 bits of the quadlet to ATF location 50h.
b) Write the second 8 bits of the quadlet to ATF location 51h.
c) Write the third 8 bits of the quadlet to ATF location 52h.
d) Write the fourth 8 bits of the quadlet to ATF location 53h.
The data is not yet confirmed for transmission.
Step 2: Writing the next (n–1) quadlets of the packet:
a) Write the first 8 bits of each quadlet to ATF location 54h.
b) Write the second 8 bits of each quadlet to ATF location 55h.
c) Write the third 8 bits of each quadlet to ATF location 56h.
d) Write the fourth 8 bits of each quadlet to ATF location 57h.
The data is not yet confirmed for transmission.
Step 3: Last (N
th
) quadlet of the packet:
a) Write the first 8 bits of the quadlet to ATF location 58h.
b) Write the second 8 bits of the quadlet to ATF location 59h.
c) Write the third 8 bits of the quadlet to ATF location 5Ah.
d) Write the fourth 8 bits of the quadlet to ATF location 5Bh.
The data is now confirmed for transmission.
To write to the ATF in a word fashion, the following steps should be followed.
Step 4: Writing the first quadlet of the packet:
a) Write the first 16 bits of the quadlet to ATF location 50h.
b) Write the second 16 bits of the quadlet to ATF location 52h.
The data is not yet confirmed for transmission.
Step 5: Writing the next (n–1) quadlets of the packet:
a) Write the first 16 bits of each quadlet to ATF location 54h.
b) Write the second 16 bits of each quadlet to ATF location 56h.
The data is not yet confirmed for transmission.
Step 6: Last (N
th
) quadlet of the packet:
a) Write the first 16 bits of the quadlet to ATF location 58h.
b) Write the second 16 bits of the quadlet to ATF location 5Ah.
The data is now confirmed for transmission.
All writes to the ATF must be quadlet aligned (i.e., only an even number of write accesses is allowed). If the
first quadlet of a packet is not written to the ATF_First location, the transmitter enters a state denoted by an
ATSTK interrupt in the interrupt register at 0Ch. An underflow of the ATF also causes an ATSTK interrupt.
When this ATF_Stuck state is entered, no asynchronous packets can be sent until the ATF is cleared by way
of the ATFCLR control bit (bit 0 in FIFO status CFR at 30h). Isochronous packets still can be sent while the
ATF is in the ATF_Stuck state.
6.3 ATF Burst Access
It is possible to perform a burst write into the address location ATF_Continue at 54h, which allows multiple
quadlets to load into ATF, but the data packet is not confirmed for transmission until an update address is
written. It is not possible to perform a burst write into the address location ATF_Continue&Update at 58h, which
loads the last quadlet of a packet into ATF and confirms the data for transmission.
Burst write accesses to the address location 5Ch or ATF_Burst_Write can write the entire packet into the ATF
from one address. The last quadlet written into ATF confirms the packet for transmission.